Lithography The ability to control interactions between features, assess image quality and compensate for lateral diffusion spreading during lithography is essential to enhancing the fundamental limits on SFR. In this project, we focus on creative, high-risk, high-payoff techniques involving metrology, control, masks, optics and resists for enhancing lithography resolution and capability.
Design Manufacturing Interface Our studies focus on improved compact models for device variations, PLL circuits and model development, proof-of-concept implementation,
new interactions of layout and process, evaluation of statistical optimization of leakage, incorporating random variability to DFM,
and design-mask interactions,
Novel Technology Our reserches focus on performing 3-D device simulations to assess the impact of LER on tri-gate bulk MOSFET performance,
assessing the relative impacts of sources of variation for tri-gate bulk MOSFETs,
completing dopant and self-diffusion in relaxed SiGe using MBE grown isotopically controlled layered structures,
Studying dopant and self-diffusion in Ge using isotopically controlled structures,
demonstrating layer transfer of Si, Ge, and strained Si/Ge on patterned uniaxial strain substrates,
electrical characterization of carrier transport and interfacial properties of SSOI and GeOI
designing and prototyping of refractive index optical stack for spectroscopy capability
and calibration of wavelength dispersion and photon intensity.
Plasma Etch Plasma instabilities and high electron temperatures in inductively driven plasma reactors are important factors limiting process reproducibility, uniformity, and selectivity during etch/deposition for larger size wafers. This project focuses on novel methods to sense, measure, model and control plasmas used in the manufacture of deep-submicron features over large substrates.
Education The educational component of our program is addressing both the UC student body, as well as the personnel of participating industries. The traditional UC model is “education through research.” Our program has followed this tradition by addressing “output-end” educational upgrades at the junior, senior and graduate years. Two major thrusts are (1) an upgraded semiconductor processing course at Berkeley, increasing capacity and making the course accessible to all science and engineering majors, and (2) the creation of new Berkeley laboratory course on semiconductor processing equipment, interdisciplinary across four engineering disciplines.
Chemical Mechanical Planarization A comprehensive model of CMP will allow the prediction of feature pattern evolution, the design of optimal process recipes and the understanding of the CMP-imposed limits on SFR. Such a model is the focus of our comprehensive, multi-disciplinary approach to this problem.
News and Highlights
IMPACT Workshop
When:
April 15, 2009: 12:00pm-5:00pm Location: AMD
Commons building in Sunnyvale Presentations and Posters
UC Impact on California's Electronics Manufacturing Industry
By Christophe Lecuyer, IUCRP
Slides Report
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