Our objective is to develop algorithms, methods, and tools that will enable IC design and manufacturing at the 22nm node and beyond. We will accomplish this by developing comprehensive process models, new robust devices, timely silicon verification techniques, and efficient design flows that guarantee both performance and yield.

We will create detailed, accurate and efficient process models for beyond-state-of-the-art photolithography, plasma etch, and chemical mechanical planarization to facilitate tighter design-manufacturing interaction. To enable better variability control in sub 32nm technologies, we will model, design, fabricate and test, robust device structures. To allow for model validation early in the design cycle, we will create novel metrology tools that will yield valuable information about the process and the nature of its variability. Finally, we will work towards integrating process variability and IC robustness into future design flows, by focusing on specific applications such as statistical performance optimization.